US 12,315,722 B2
Method for making a radio frequency silicon-on-insulator (RFSOI) wafer including a superlattice
Nyles Wynn Cody, Tempe, AZ (US); Keith D. Weeks, Chandler, AZ (US); Robert Michael Vyne, Chandler, AZ (US); and Robert J. Stephenson, Duxford (GB)
Assigned to ATOMERA INCORPORATED, Los Gatos, CA (US)
Filed by Atomera Incorporated, Los Gatos, CA (US)
Filed on Mar. 14, 2024, as Appl. No. 18/604,620.
Claims priority of provisional application 63/490,119, filed on Mar. 14, 2023.
Prior Publication US 2024/0312781 A1, Sep. 19, 2024
Int. Cl. H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 21/324 (2006.01)
CPC H01L 21/02488 (2013.01) [H01L 21/0245 (2013.01); H01L 21/3065 (2013.01); H01L 21/324 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method for making a semiconductor device comprising:
in an epitaxial deposition tool,
performing an anneal on a semiconductor on insulator (SOI) substrate comprising a first semiconductor layer, an insulating layer on the first semiconductor layer, and a second semiconductor layer on the insulating layer, the second semiconductor layer having a first thickness,
performing an in-situ etch at a temperature in a range of 950° C. to 1050° C. to reduce the second semiconductor layer to a second thickness less than the first thickness and with a haze in a range of 0.235 to 0.5 PPM, and
forming a superlattice layer on the second semiconductor layer, the superlattice layer comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.