US 12,315,580 B2
Built-in self-test circuitry
William Yu, Boise, ID (US); Daniele Balluchi, Cernusco Sul Naviglio (IT); Danilo Caraccio, Milan (IT); Thomas T. Tangelder, Boise, ID (US); Jacob S. Robertson, Caldwell, ID (US); James G. Steele, Boise, ID (US); and Joemar Sinipete, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 13, 2022, as Appl. No. 17/944,135.
Prior Publication US 2024/0087663 A1, Mar. 14, 2024
Int. Cl. G11C 16/04 (2006.01); G11C 29/02 (2006.01); G11C 29/36 (2006.01); G11C 29/42 (2006.01)
CPC G11C 29/36 (2013.01) [G11C 29/022 (2013.01); G11C 29/42 (2013.01); G11C 2029/3602 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of memory devices; and
a controller coupled to the plurality of memory devices and comprising built-in self-test (BIST) circuitry comprising a plurality of registers configured to store a number of burst patterns,
wherein the BIST circuitry is configured to perform a BIST operation on the plurality of memory devices contemporaneously and using the number of burst patterns; and
comparison circuity coupled to the BIST circuitry configured to:
compare data read from the plurality of memory devices with a selected read burst pattern; and
provide an indication of whether the data read from the plurality of memory devices corresponds to the selected read burst pattern.