US 12,315,575 B2
Boost voltage modulated corrective read
Nagendra Prasad Ganesh Rao, Folsom, CA (US); Dheeraj Srinivasan, San Jose, CA (US); Paing Z. Htet, Union City, CA (US); Sead Zildzic, Jr., Folsom, CA (US); and Violante Moschiano, Avezzano (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 10, 2023, as Appl. No. 18/132,489.
Claims priority of provisional application 63/335,788, filed on Apr. 28, 2022.
Prior Publication US 2023/0352098 A1, Nov. 2, 2023
Int. Cl. G11C 7/00 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 16/0483 (2013.01); G11C 16/30 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array comprising:
a set of target cells connected to a target wordline;
at least one wordline adjacent to the target wordline; and
for each target cell of the set of target cells, a respective group of adjacent cells adjacent to the target cell, wherein each group of adjacent cells comprises at least one cell connected to the at least one wordline; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing a read operation to be initiated with respect to the set of target cells;
obtaining cell state information for each group of adjacent cells;
for each target cell of the set of target cells, determining a state information bin of a set of state information bins based on the cell state information for its respective group of adjacent cells; and
assigning each target cell of the set of target cells to the respective state information bin, wherein each state information bin of the set of state information bins defines a respective boost voltage level offset to be applied to perform boost voltage modulation.