| CPC G11C 16/16 (2013.01) [G11C 16/102 (2013.01); G11C 16/12 (2013.01)] | 9 Claims |
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1. A semiconductor element memory device comprising a block constituted by a plurality of memory cells arranged in a matrix on a substrate, each of the memory cells included in the block comprising:
a semiconductor body formed to stand on the substrate in a vertical direction relative to the substrate or extend in a horizontal direction relative to the substrate;
a first impurity region and a second impurity region formed to be disposed, respectively, at ends of the semiconductor body;
a gate insulator layer formed in contact with a side surface of the semiconductor body between the first impurity region and the second impurity region;
a first gate conductor layer formed to at least partially cover the gate insulator layer; and
a second gate conductor layer formed adjacent to the first gate conductor layer in contact with a side surface of the gate insulator layer, wherein in each of the memory cells,
voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region are controlled to retain, inside the semiconductor body, a group of positive holes, which are generated by an impact ionization phenomenon or a gate-induced drain leakage current,
a memory write operation is performed in which a voltage of the semiconductor body is made equal to a first data retention voltage that is higher than the voltage of one of the first impurity region or the second impurity region or the voltages of both of the first impurity region and the second impurity region by a built-in voltage,
a memory erase operation is performed in which the voltage of the semiconductor body is controlled so as to be higher than the first data retention voltage with first capacitive coupling between the first gate conductor layer and the semiconductor body and second capacitive coupling between the second gate conductor layer and the semiconductor body, and a group of remaining positive holes among the group of positive holes are discharged from inside the semiconductor body through one or both of the first impurity region and the second impurity region until the voltage of the semiconductor body becomes equal to a voltage higher than the voltage of one of the first impurity region or the second impurity region or the voltages of both of the first impurity region and the second impurity region by the built-in voltage, and
further wherein the voltage of the semiconductor body is made equal to a second data retention voltage lower than the first data retention voltage with the first capacitive coupling and the second capacitive coupling,
the voltage of the semiconductor body in each of the plurality of memory cells in the block is equal to the first data retention voltage or the second data retention voltage at a first time,
at a second time after a lapse of time since the first time, a memory re-write operation is performed for the semiconductor body, in the block, that is at a voltage equal to the first data retention voltage at the first time to return the voltage of the semiconductor body to a voltage close to the first data retention voltage, and
at a third time after a lapse of time since the first time, a memory re-erase operation is performed for the semiconductor body, in the block, that is at a voltage equal to the second data retention voltage at the first time to return the voltage of the semiconductor body to a voltage close to the second data retention voltage.
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