US 12,315,569 B2
Differential memory cell array structure for multi-time programming non-volatile memory
Jui-Ming Kuo, Hsinchu County (TW); Hung-Yi Liao, Hsinchu County (TW); Wei-Ren Chen, Hsinchu County (TW); and Wein-Town Sun, Hsinchu County (TW)
Assigned to EMEMORY TECHNOLOGY INC., Hsin-Chu (TW)
Filed by eMemory Technology Inc., Hsin-Chu (TW)
Filed on Mar. 10, 2022, as Appl. No. 17/691,161.
Claims priority of provisional application 63/221,013, filed on Jul. 13, 2021.
Prior Publication US 2023/0014498 A1, Jan. 19, 2023
Int. Cl. G11C 16/14 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); H10B 41/00 (2023.01)
CPC G11C 16/14 (2013.01) [G11C 16/0441 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); H10B 41/00 (2023.02)] 7 Claims
OG exemplary drawing
 
1. A differential memory cell array structure comprising a first differential memory cell, wherein the first differential memory cell comprises:
a first select transistor, wherein a first source/drain terminal of the first select transistor is connected to a first source line, a gate terminal of the first select transistor is connected to a first word line, and a body terminal of the first select transistor receives a first well region voltage;
a first floating gate transistor, wherein a first drain/source terminal of the first floating gate transistor is connected to a second drain/source terminal of the first select transistor, a second drain/source terminal of the first floating gate transistor is coupled to a first bit line, and a body terminal of the first floating gate transistor receives the first well region voltage;
a first capacitor, wherein a first terminal of the first capacitor is connected to a floating gate of the first floating gate transistor, and a second terminal of the first capacitor is connected to a first erase line;
a second select transistor, wherein a first source/drain terminal of the second select transistor is connected to the first source line, a gate terminal of the second select transistor is connected to the first word line, and a body terminal of the second select transistor receives the first well region voltage;
a second floating gate transistor, wherein a first drain/source terminal of the second floating gate transistor is connected to a second drain/source terminal of the second select transistor, a second drain/source terminal of the second floating gate transistor is coupled to a first inverted bit line, and a body terminal of the second floating gate transistor receives the first well region voltage; and
a second capacitor, wherein a first terminal of the second capacitor is connected to a floating gate of the second floating gate transistor, and a second terminal of the second capacitor is connected to the first erase line;
wherein the differential memory cell array structure further comprises:
a semiconductor substrate;
a first N-well region formed under a surface of the semiconductor substrate;
a first P-well region formed under the surface of the semiconductor substrate;
a first gate structure covered on the first N-well region;
a second gate structure covered on the first N-well region and the first P-well region;
a third gate structure covered on the first N-well region and the first P-well region;
a first p-type doped region formed in the first N-well region, and located beside a first side of the first gate structure;
a second p-type doped region formed in the first N-well region, and arranged between a second side of the first gate structure and a first side of the second gate structure;
a third p-type doped region formed in the first N-well region, and located beside a second side of the second gate structure;
a fourth p-type doped region formed in the first N-well region, and located beside the first side of the first gate structure;
a fifth p-type doped region formed in the first N-well region, and arranged between the second side of the first gate structure and a first side of the third gate structure;
a sixth p-type doped region formed in the first N-well region, and located beside a second side of the third gate structure; and
a first n-type doped region formed in the first P-well region,
wherein a portion of the second gate structure is extended to the first P-well region and located beside the first n-type doped region, and a portion of the third gate structure is extended to the first P-well region and located beside the first n-type doped region,
wherein the first select transistor is defined by the first N-well region, the first p-type doped region, the second p-type doped region and the first gate structure collaboratively, the first floating gate transistor is defined by the first N-well region, the second p-type doped region, the third p-type doped region and the second gate structure collaboratively, the first capacitor is defined by the second gate structure and the first n-typed doped region collaboratively, the second select transistor is defined by the first N-well region, the fourth p-typed doped region, the fifth p-typed doped region and the first gate structure collaboratively, the second floating gate transistor is defined by the first N-well region, the fifth p-type doped region, the sixth p-type doped region and the third gate structure collaboratively, and the second capacitor is defined by the third gate structure and the first n-type doped region collaboratively.