US 12,315,549 B2
Semiconductor memory device for performing remaining bank refresh operation and refresh method thereof
Jongpil Son, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 4, 2023, as Appl. No. 18/295,285.
Claims priority of application No. 10-2022-0138466 (KR), filed on Oct. 25, 2022.
Prior Publication US 2024/0135982 A1, Apr. 25, 2024
Prior Publication US 2024/0233802 A9, Jul. 11, 2024
Int. Cl. G11C 11/00 (2006.01); G11C 11/406 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/40618 (2013.01) [G11C 11/40615 (2013.01); G11C 11/4087 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a memory cell array including a plurality of memory banks;
a command decoder configured to decode a per-bank refresh command and a remaining bank refresh command;
a refresh controller configured to:
perform a per-bank refresh operation for refreshing at least one memory bank among the plurality of memory banks based on a decoding result of the per-bank refresh command of the command decoder; and
perform a remaining bank refresh operation for refreshing remaining memory banks other than the at least one memory bank among the plurality of memory banks, in response to the remaining bank refresh command during one refresh cycle; and
a refresh status register configured to update whether each of the plurality of memory banks has been refreshed during the one refresh cycle.