US 12,315,548 B2
Bank selection for refreshing
Yang Lu, Boise, ID (US); and Kang-Yong Kim, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 22, 2022, as Appl. No. 17/871,752.
Prior Publication US 2024/0029778 A1, Jan. 25, 2024
Int. Cl. G11C 11/406 (2006.01); G11C 16/34 (2006.01)
CPC G11C 11/40618 (2013.01) [G11C 11/406 (2013.01); G11C 11/40622 (2013.01); G11C 16/3418 (2013.01); G11C 2211/4013 (2013.01); G11C 2211/4062 (2013.01); G11C 2211/4063 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
mode registers;
a plurality of banks of a memory device; and
refresh bank circuitry coupled to the plurality of banks and the mode registers and configured to:
receive a refresh command, wherein the refresh command comprises selector bits;
receive mode register bits from the mode registers; and
refresh a number of banks from the plurality of banks utilizing the mode register bits and the selector bits, wherein a first number of banks from the plurality of banks are refreshed utilizing a first value of the mode register bits, a first value of the selector bits and a portion of a plurality of address bits, wherein the first value of the mode register bits identifies a first bit of the plurality of address bits to not utilize.