US 12,315,469 B2
Gate drive circuit, drive device and display device
Jianlei Li, Guangdong (CN); and Haoxuan Zheng, Guangdong (CN)
Assigned to HKC CORPORATION LIMITED, Shenzheng (CN)
Appl. No. 17/800,341
Filed by HKC CORPORATION LIMITED, Guangdong (CN)
PCT Filed Dec. 23, 2021, PCT No. PCT/CN2021/140936
§ 371(c)(1), (2) Date Aug. 17, 2022,
PCT Pub. No. WO2022/199167, PCT Pub. Date Sep. 29, 2022.
Claims priority of application No. 202110317868.4 (CN), filed on Mar. 25, 2021.
Prior Publication US 2024/0296808 A1, Sep. 5, 2024
Int. Cl. G09G 3/36 (2006.01); G11C 19/28 (2006.01)
CPC G09G 3/3677 (2013.01) [G11C 19/287 (2013.01); G09G 3/3614 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0291 (2013.01); G09G 2340/0435 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A gate drive circuit, applied to a display panel, and comprising:
m switch groups, each switch group comprising n first switch units, wherein an output end of each first switch units is configured in connection with a gate-line of the display panel, controlled ends of the n first switch units in each switch group are connected in common to form a first controlled node, and input ends of i-th first switch units in the m switch groups are connected in common to form an i-th input node, wherein m and n are positive integers, i=1, 2, . . . , n;
n first shift registers, which are connected in sequence and are respectively connected to the n input nodes in a one-to-one correspondence, wherein the n first shift registers are configured, according to a first start signal and a first clock pulse signal, to output a first row-scan signal to each of the input nodes in turn and loop; and
m second shift registers, which are connected in sequence and are respectively connected to m first controlled nodes in a one-to-one correspondence, wherein the m second shift registers are configured, according to a second start signal and a second clock pulse signal, to output a second row-scan signal to each of the first controlled nodes in turn, so as to sequentially trigger on the n first switch units connected to each of the first controlled nodes, so that the first row-scan signal is fed back to each of the gate-lines in turn,
wherein the gate drive circuit further comprises a precharge circuit, and the precharge circuit comprises m−1 first unidirectional conduction units and m−1 second unidirectional conduction units;
the m−1 first unidirectional conduction units are respectively connected one by one between adjacent signal output ends of the m second shift registers, and each of the second unidirectional conduction units is respectively connected to the output ends of the second shift registers range from a 2-nd one to a m-th one in a unidirectional manner, a positive input end of each first unidirectional conduction unit is connected to an output end of a previous second shift register or a positive output end of one second unidirectional conduction unit, and a negative output end of each first unidirectional conduction unit is connected to a negative output end of another second unidirectional conduction unit; and
each of the first unidirectional conduction units is configured to synchronously output the second row-scan signal output from the previous second shift register to the controlled node where a next second shift register is connected, when the second row-scan signal is output from the previous second shift register, which enables two thin film transistors in n adjacent rows in the display panel to be turned on to perform charging and precharging of data signals.