US 12,315,464 B2
Display panel and display device
Nana Xiong, Shanghai (CN); and Jujian Fu, Shanghai (CN)
Assigned to SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD., Shanghai (CN)
Filed by Shanghai Tianma Micro-Electronics Co., Ltd., Shanghai (CN)
Filed on Apr. 27, 2023, as Appl. No. 18/308,446.
Application 18/308,446 is a continuation of application No. 17/565,255, filed on Dec. 29, 2021, granted, now 11,670,246.
Application 17/565,255 is a continuation of application No. 17/332,222, filed on May 27, 2021, granted, now 11,250,790, issued on Feb. 15, 2022.
Claims priority of application No. 202110226111.4 (CN), filed on Mar. 1, 2021.
Prior Publication US 2023/0260470 A1, Aug. 17, 2023
Int. Cl. G09G 3/3291 (2016.01)
CPC G09G 3/3291 (2013.01) [G09G 2300/08 (2013.01); G09G 2310/065 (2013.01)] 18 Claims
OG exemplary drawing
 
18. A display device, comprising a display panel, wherein the display panel comprises a plurality of pixel circuits and a light emitting element;
wherein at least one pixel circuit of the plurality of pixel circuits each comprises a driving transistor, a second transistor, a third transistor, and a first light-emission controlling module, wherein the second transistor is connected between a data line and a source of the driving transistor and is configured to provide a data signal;
wherein the third transistor is connected between a voltage adjusting signal line and the source of the driving transistor and is configured to provide an adjusting voltage;
wherein the first light-emission controlling module is connected between a first power supply terminal and the source of the driving transistor and is configured to provide a power supply voltage;
wherein the power supply voltage provided by the first power supply terminal is VP, and the adjusting voltage is VJ, where VP<VJ≤VP+3.5V, and/or VP+1V<VJ;
wherein adjusting signal input terminals of at least two third transistors of at least two pixel circuits of the pixel circuits in one pixel column are connected to a same voltage adjusting signal line, and adjusting signal input terminals of at least two third transistors of at least two pixel circuits of the pixel circuits in one pixel row are connected to a same voltage adjusting signal line;
wherein an operation process of the display panel comprises a data writing phase and a reset and adjustment phase;
wherein, during the data writing phase, the second transistor is turned on, the data line is configured to provide a data signal to the source of the driving transistor, the data signal is VData, a gate of the driving transistor is configured to receive the data signal, and a voltage of the gate of the driving transistor is VData+Vth, where Vth denotes a threshold voltage of the driving transistor;
wherein, during the reset and adjustment phase, the third transistor is turned on, the voltage adjusting signal line is configured to provide an adjusting voltage to the source of the driving transistor, a voltage of the source of the driving transistor is VJ, and the voltage of the gate of the driving transistor remains VData+Vth; and
wherein VData+Vth−VJ≤−2V.