US 12,315,420 B2
Gate driver and display apparatus including the same
Cholho Kim, Suwon-si (KR); Gunwoo Yang, Seoul (KR); Hyunyoung Choi, Seoul (KR); Jihoon Yang, Seoul (KR); and Yongwoo Lee, Gimpo-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed by SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed on Sep. 12, 2022, as Appl. No. 17/931,311.
Application 17/931,311 is a continuation of application No. 15/412,691, filed on Jan. 23, 2017, granted, now 11,443,681.
Claims priority of application No. 10-2016-0024645 (KR), filed on Feb. 29, 2016.
Prior Publication US 2023/0005412 A1, Jan. 5, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/20 (2006.01); G09G 3/3266 (2016.01); G09G 3/36 (2006.01); G11C 19/28 (2006.01); G09G 3/296 (2013.01)
CPC G09G 3/2092 (2013.01) [G09G 3/3266 (2013.01); G09G 3/3677 (2013.01); G11C 19/28 (2013.01); G09G 3/296 (2013.01); G09G 3/3659 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0223 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A gate driver comprising:
a first clock terminal;
a second clock terminal;
a voltage terminal;
a gate output terminal;
a pull-up-pull-down sub-circuit connected to the first clock terminal and the gate output terminal; and
a pull-down boosting sub-circuit connected to the first clock terminal, the second clock terminal and the voltage terminal,
wherein the pull-down boosting sub-circuit comprises a transistor that includes a first electrode directly connected to the voltage terminal, a second electrode directly connected to the first clock terminal and a control electrode connected to the second clock terminal.