US 12,315,418 B2
Display panel redundancy schemes
Kapil V. Sakariya, Los Altos, CA (US); Tore Nauta, Santa Cruz, CA (US); Hopil Bae, Sunnyvale, CA (US); Henry C. Jen, Los Altos, CA (US); James E. Pedder, Cupertino, CA (US); Sunggu Kang, San Jose, CA (US); Shingo Hatanaka, San Jose, CA (US); Xiang Lu, Campbell, CA (US); Mahdi Farrokh Baroughi, Santa Clara, CA (US); Hasan Akyol, Mountain View, CA (US); Saif Choudhary, San Jose, CA (US); and Ion Bita, Santa Clara, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Dec. 15, 2022, as Appl. No. 18/066,725.
Application 18/066,725 is a continuation of application No. 17/338,475, filed on Jun. 3, 2021, granted, now 11,568,789.
Application 17/338,475 is a continuation of application No. 16/688,750, filed on Nov. 19, 2019, granted, now 11,056,041, issued on Jul. 6, 2021.
Application 16/688,750 is a continuation of application No. 15/576,237, granted, now 10,535,296, issued on Jan. 14, 2020, previously published as PCT/US2016/034878, filed on May 27, 2016.
Claims priority of provisional application 62/173,769, filed on Jun. 10, 2015.
Prior Publication US 2023/0222955 A1, Jul. 13, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/20 (2006.01); G09G 3/32 (2016.01)
CPC G09G 3/2088 (2013.01) [G09G 3/2014 (2013.01); G09G 3/32 (2013.01); G09G 2300/0413 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0804 (2013.01); G09G 2300/0857 (2013.01); G09G 2310/027 (2013.01); G09G 2310/0272 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/08 (2013.01); G09G 2330/08 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A display panel comprising:
an array of driver chips arranged in rows and columns, each driver chip including digital logic coupled with analog circuitry that includes a plurality of switches and plurality of current sources;
wherein each driver chip is connected with a corresponding plurality of light emitting diodes (LEDs) forming a plurality of pixels;
wherein each pixel includes a plurality of subpixels, each subpixel including a primary LED connected to a corresponding driver chip and a spare LED connected to the corresponding driver chip; and
wherein the primary LED and the spare LED are coupled to a common switch of the plurality of switches of the driver chip, the common switch is coupled to a common current source of the plurality of current sources that corresponds to the common switch, and the common switch is a transistor that causes the common current source to illuminate either the primary LED or the spare LED;
wherein the digital logic includes a counter, a plurality of comparators, and a register; wherein the common switch is coupled to a common comparator of the plurality of comparators.