US 12,315,066 B2
Graphics processing method and system
Xile Yang, Zhuhai (CN); and Hai Ao, Zhuhai (CN)
Filed by INNOSILICON MICROELECTRONICS (ZHUHAI) CO., LTD., Zhuhai (CN)
Filed on Mar. 25, 2023, as Appl. No. 18/190,084.
Application 18/190,084 is a continuation of application No. PCT/CN2022/140670, filed on Dec. 21, 2022.
Claims priority of application No. 202211013176.1 (CN), filed on Aug. 23, 2022.
Prior Publication US 2024/0070962 A1, Feb. 29, 2024
Int. Cl. G06T 15/00 (2011.01)
CPC G06T 15/005 (2013.01) 20 Claims
OG exemplary drawing
 
1. A graphics processing system comprising multiple cores with a master mode core and at least one slave mode core, wherein the master mode core is configured to construct primitives according to input geometry data, split the constructed primitives into primitive core groups, and distribute the primitive core groups to the master mode core and the at least one slave mode core; and the master mode core and the at least one slave mode core are configured to process the distributed primitive core groups to obtain a rendered image; wherein:
each of the multiple cores comprises a geometry processing system and a fragment processing system; and the geometry processing system of each of the multiple cores comprises an input assembler module, at least one geometry processing pipeline, and a tiling module; wherein:
the input assembler module of the master mode core is configured to construct the primitives according to the input geometry data, split the constructed primitives into the primitive core groups, and distribute the primitive core groups to the input assembler module of each of the multiple cores;
the input assembler module of each of the multiple cores is configured to send the distributed primitive core groups to the corresponding at least one geometry processing pipeline;
the at least one geometry processing pipeline of each of the multiple cores is configured to process the distributed primitive core groups to make sure all primitives of the primitive core groups are in screen view space;
the tiling module of each of the multiple cores is configured to tile the primitive core groups from the corresponding at least one geometry processing pipeline into multiple tiles in the screen view space, and generate a tiling display list for each tile; and
the fragment processing system of each of the multiple cores is configured to merge the tiling display lists generated by the geometry processing systems of the multiple cores into one single tiling display list, and render the tile according to the merged tiling display list to obtain the rendered image.