US 12,314,845 B2
Field programmable gate array (FPGA) based neuromorphic computing architecture
Dhaval Shah, Thane West (IN); Sounak Dey, Kolkata (IN); Meripe Ajay Kumar, Bangalore (IN); Manoj Nambiar, Thane West (IN); and Arpan Pal, Kolkata (IN)
Assigned to Tata Consultancy Services Limited, Mumbai (IN)
Filed by Tata Consultancy Services Limited, Mumbai (IN)
Filed on Mar. 2, 2022, as Appl. No. 17/684,937.
Claims priority of application No. 202121047012 (IN), filed on Oct. 14, 2021.
Prior Publication US 2023/0122192 A1, Apr. 20, 2023
Int. Cl. G06N 3/063 (2023.01); G06N 3/049 (2023.01); G06N 3/065 (2023.01)
CPC G06N 3/065 (2023.01) [G06N 3/049 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A field programmable gate array (FPGA) neuromorphic architecture-based method for computing comprising:
receiving a synaptic weight and a data set associated with an application, wherein the data set comprises a plurality of features and the synaptic weight is a pre-trained parameter;
generating a neuromorphic FPGA circuit comprising a memory and a plurality of neurons based on a Spiking Neural Network (SNN) technique, where in the generation of the neuromorphic FPGA circuit is characterized by comprising the following steps:
transferring the synaptic weight to the memory; and
generating a plurality of neurons based on the plurality of features, wherein each neuron among the plurality of neurons comprises a Multiply and Accumulate (MA) layer, a Registered Adder Tree (RAT) layer and a Leaky Integrate and Fire (LIF) layer;
optimizing via the one or more hardware processors, the neuromorphic FPGA circuit based on the plurality of features to obtain a neuromorphic FPGA architecture, wherein the optimization comprises an arrangement of the generated plurality of neurons in a modular and a parallel fashion based on the plurality of features;
receiving a plurality of input spikes, wherein the plurality of input spikes is associated with the data set; and
computing a plurality of output spikes for the plurality of input spikes using the neuromorphic FPGA architecture, wherein the plurality of output spikes is utilized for classification and inferencing of the data set,
wherein each neuron among the plurality of neurons is interconnected with other neurons of a backward or a forward layer only through a plurality of synapses in multiple layers, and each of the neuron is mutually independent.