| CPC G06N 3/04 (2013.01) [G06F 17/153 (2013.01); G06F 17/16 (2013.01); G06N 3/08 (2013.01); G06T 9/002 (2013.01); G06F 9/3001 (2013.01)] | 20 Claims |

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1. A processor, comprising:
a register for storing an arrangement of weights;
a buffer for storing an arrangement of features;
a first multiplier; and
a second multiplier;
wherein the first multiplier is configured to perform a convolution of an arrangement of the features with an arrangement of weights, the performing of the convolution comprising:
forming a product of the arrangement of weights with a first portion of the arrangement of features;
forming a product of the arrangement of weights with a second portion of the arrangement of features, the second portion being offset from the first portion by n arrangement of elements in a first direction, n being a positive integer; and
forming a product of the arrangement of weights with a third portion of the arrangement of features, the third portion being offset from the second portion by one arrangement of elements in a second direction, perpendicular to the first direction,
wherein the second portion and the third portion are spaced apart from an end of a row of the arrangement of features.
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