| CPC G06F 9/30145 (2013.01) [G06F 9/30007 (2013.01); G06F 9/3001 (2013.01); G06F 9/30032 (2013.01); G06F 9/30043 (2013.01); G06F 9/30101 (2013.01); G06F 9/30105 (2013.01); G06F 9/3818 (2013.01); G06F 9/44505 (2013.01); G06F 12/0246 (2013.01); G06F 12/0292 (2013.01); G06F 16/322 (2019.01); G06F 16/41 (2019.01); G06F 16/9017 (2019.01); G11C 11/409 (2013.01); G06F 3/0647 (2013.01); G06F 9/30167 (2013.01); G06F 9/355 (2013.01); G06F 12/0811 (2013.01)] | 20 Claims |

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1. A device, comprising:
a memory;
a processor functional unit coupled to the memory; and
a decoder coupled to the processor functional unit and configured to:
receive a table write instruction that includes a first field specifying a base address of a plurality of tables in the memory, and a second field specifying a plurality of data elements; and
in response to receiving the table write instruction, cause the processor functional unit to write each data element of the plurality of data elements to a corresponding table of the plurality of tables based on the base address of the plurality of tables.
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