US 12,314,683 B2
Methods and systems with bitwise pooling operations
Arnab Roy, Bengaluru (IN); Kiran Kolar Chandrasekharan, Bengaluru (IN); and Sehwan Lee, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 26, 2021, as Appl. No. 17/186,161.
Claims priority of application No. 202041008134 (IN), filed on Feb. 26, 2020; and application No. 10-2021-0025627 (KR), filed on Feb. 25, 2021.
Prior Publication US 2021/0263738 A1, Aug. 26, 2021
Int. Cl. G06F 7/544 (2006.01); G06F 9/30 (2018.01)
CPC G06F 7/544 (2013.01) [G06F 9/30018 (2013.01); G06F 9/30038 (2023.08)] 23 Claims
OG exemplary drawing
 
1. A processor-implemented method for performing pooling operations, the method comprising:
performing, using logic gates of a first data path of logic circuitry of fused hardware, either one or both of a first maximum pooling operation and a first minimum pooling operation in a bitwise manner on respective 2-bit ternary data of a ternary vector;
performing, using logic gates of a second data path of the logic circuitry including one or more of the logic gates of the first data path, either one or both of a second maximum pooling operation and a second minimum pooling operation of respective 1-bit binary data of a binary vector; and
performing, using the first data path and the second data path of the logic circuitry, a third pooling operation in the bitwise manner on an input ternary vector or an input binary vector.