| CPC G06F 30/398 (2020.01) [G06F 30/367 (2020.01); G06F 30/392 (2020.01); G06F 2119/02 (2020.01)] | 10 Claims |

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1. A computer-implemented method for use in an electronic design environment comprising:
receiving, using at least one processor, an electronic design layout;
performing parasitic extraction on the electronic design layout;
extracting an electromagnetic model from the electronic design layout;
reconnecting at least one coupling capacitor associated with a net of the electromagnetic model;
performing a simulation including the reconnected at least one coupling capacitor, wherein reconnecting at least one coupling capacitor includes reconnecting to an electromagnetic simulator network prior to solving for one or more s-parameters;
defining one or more trace through cells, wherein a trace through cell is defined using at least one of a text file, an environmental variable, net tracing, or DC path information;
automatically detecting the one or more trace through cells; and
reconnecting a capacitance for one or more embedded nets that connect to the trace through cells.
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