US 12,314,652 B2
Methods and non-transitory computer-readable media for inter-metal dielectric reliability check
Hsien Yu Tseng, Miaoli County (TW); and Wei-Ming Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Feb. 16, 2022, as Appl. No. 17/673,205.
Prior Publication US 2023/0259688 A1, Aug. 17, 2023
Int. Cl. G06F 30/398 (2020.01); G06F 30/392 (2020.01); G06F 119/06 (2020.01)
CPC G06F 30/398 (2020.01) [G06F 30/392 (2020.01); G06F 2119/06 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving an electronic layout, the electronic layout including a first plurality of electrical components in a first layer;
determining an internal voltage difference within each electrical component in the first layer based on parasitic effect;
generating a simulation voltage value for each electrical component in the first layer based on the internal voltage differences; and
tagging a pair of electrical components in the first layer when a first voltage difference between the pair of electrical components exceeds a first voltage threshold, wherein the first voltage difference is determined based on the simulation voltage value of each electrical component, wherein:
the electronic layout includes a second plurality of electrical components in a second layer, the second layer being adjacent to the first layer;
determining an internal voltage difference within each electrical component in the second layer based on parasitic effect;
generating a simulation voltage value for each electrical component in the second layer based on the internal voltage differences; and
tagging a first electrical component in the first layer and a second electrical component in the second layer when a second voltage difference between the first electrical component in the first layer and the second electrical component in the second layer exceeds a second voltage threshold.