US 12,314,588 B2
System and method for coalesced multicast data transfers over memory interfaces
Johnathan Alsop, Bellevue, WA (US); Nuwan Jayasena, Santa Clara, CA (US); Shaizeen Aga, Santa Clara, CA (US); and Andrew McCrabb, Ann Arbor, MI (US)
Assigned to ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Oct. 23, 2023, as Appl. No. 18/492,081.
Application 18/492,081 is a continuation of application No. 17/218,700, filed on Mar. 31, 2021, granted, now 11,803,311.
Prior Publication US 2024/0045606 A1, Feb. 8, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/064 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0644 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory module comprising:
a processor interface configured to communicate with a processor;
a 3-D stacked memory comprising a plurality of memory submodules, each submodule comprising a respective short data link that communicates short data words;
multicast coalesce logic, configured to retrieve short data words from each of the plurality of memory submodules, coalesce the retrieved short data words into multicast coalesced block data and transfer, via the processor interface, the multicast coalesced block data over a memory channel that has a larger channel width than each of the respective short data links.