US 12,314,578 B2
Memory, controller, memory system and operation method of memory system
Jin Ho Baek, Gyeonggi-do (KR); and Young Pyo Joo, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Apr. 21, 2023, as Appl. No. 18/304,345.
Claims priority of application No. 10-2022-0119236 (KR), filed on Sep. 21, 2022; and application No. 10-2023-0026607 (KR), filed on Feb. 28, 2023.
Prior Publication US 2024/0094927 A1, Mar. 21, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0625 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 2212/7202 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A controller comprising:
a data separator disposed within the controller and configured to separate host write data into upper data and lower data, wherein the host write data include a plurality of rational numbers each of which includes an integer part and a decimal part, and the data separator separates the host write data into the lower data including some of the decimal part, and the upper data including the integer part and the rest of the decimal part;
an address generator disposed within the controller and configured to generate a first address and a second address based on a host address;
a command generator disposed within the controller and configured to generate one or more first commands for writing the upper data into a first storage region that is selected based on the first address in a memory, and one or more second commands for writing the lower data into a second storage region that is selected based on the second address in the memory; and
a control block configured to control the address generator and the command generator to make a difference in power consumption between the first storage region and the second storage region,
wherein, in maintaining by the control block a higher accuracy for the upper data, the first storage region containing the upper data has a higher power consumption than the second storage containing the lower data.