US 12,314,566 B2
Read disturb management for memory
Francesco Basso, Portici (IT); Francesco Falanga, Quarto (IT); Alberto Sassara, Naples (IT); and Massimo Iaculo, San Marco Evangelista (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 12, 2022, as Appl. No. 17/931,416.
Prior Publication US 2024/0086070 A1, Mar. 14, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0673 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
read data from a first page of a virtual block of the one or more memory devices, wherein the virtual block comprises a plurality of pages that comprises the first page and a second page;
determine whether data stored to the second page of the virtual block comprises one or more errors based at least in part on determining that the data read from the first page of the virtual block comprises one or more errors, wherein the one or more errors of the second page are associated with a shift in a threshold voltage of one or more memory cells of the second page, wherein the shift in the threshold voltage is based at least in part on reading the data from the first page;
determine that data stored to the plurality of pages of the virtual block comprise one or more errors based at least in part on determining that the data stored to the second page of the virtual block comprises one or more errors, wherein the plurality of pages comprise the second page;
postpone refreshing the plurality of pages of the virtual block based at least in part on a quantity of the plurality of pages satisfying a threshold quantity of pages; and
refresh the second page of the virtual block based at least in part on postponing refreshing the plurality of pages of the virtual block.