US 12,314,452 B2
Detecting possible security violations in an integrated circuit
Brian Taylor Brunn, Austin, TX (US)
Assigned to Silicon Laboratories Inc., Austin, TX (US)
Filed by Silicon Laboratories Inc., Austin, TX (US)
Filed on Nov. 28, 2023, as Appl. No. 18/521,023.
Application 18/521,023 is a division of application No. 17/210,823, filed on Mar. 24, 2021, granted, now 11,886,621.
Prior Publication US 2024/0095407 A1, Mar. 21, 2024
Int. Cl. G06F 21/72 (2013.01); G06F 1/08 (2006.01)
CPC G06F 21/725 (2013.01) [G06F 1/08 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a process monitor circuit to receive a reference clock signal and generate a first signal using the reference clock signal;
a comparator coupled to the process monitor circuit, the comparator to receive the first signal and a reference signal, and output a comparison signal based at least in part on a comparison between the first signal and the reference signal; and
a controller coupled to the comparator, wherein the controller is to detect a potential security violation when the comparison signal departs from an expected range.