US 12,314,217 B2
Hybrid hardware accelerator and programmable array architecture
Zoran Zivkovic, Hertogenbosch (NL); Kameran Azadet, San Ramon, CA (US); Kannan Rajamani, Basking Ridge, NJ (US); and Thomas Smith, Colmar, PA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2021, as Appl. No. 17/560,637.
Prior Publication US 2023/0205730 A1, Jun. 29, 2023
Int. Cl. G06F 15/80 (2006.01); G06F 17/11 (2006.01)
CPC G06F 15/8092 (2013.01) [G06F 17/11 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A system on a chip (SoC), comprising:
an array of processing elements, each one of the processing elements being configured to perform processing operations on an array of data samples;
a hardware accelerator; and
a data interface comprising a buffer, the data interface being coupled to the array of processing elements and to the hardware accelerator,
wherein the data interface is configured to transfer the array of data samples from the array of processing elements to the hardware accelerator by storing the array of data samples at an address location in the buffer based upon a respective one of the processing elements from which the array of data samples was received, and
wherein the hardware accelerator is configured to compute, based upon the transferred array of data samples, a set of computed terms in accordance with a predetermined processing function to generate processed data samples including the set of computed terms.