US 12,314,216 B2
Digital pre-distortion (DPD) adaptation using a hybrid hardware accelerator and programmable array architecture
Zoran Zivkovic, Hertogenbosch (NL); Kameran Azadet, San Ramon, CA (US); Kannan Rajamani, Basking Ridge, NJ (US); and Thomas Smith, Colmar, PA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2021, as Appl. No. 17/560,685.
Prior Publication US 2023/0205727 A1, Jun. 29, 2023
Int. Cl. G06F 9/38 (2018.01); G06F 1/26 (2006.01); G06F 15/80 (2006.01)
CPC G06F 15/80 (2013.01) [G06F 1/26 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A system on a chip (SoC), comprising:
an array of processing elements, each one of the processing elements being configured to perform processing operations on an array of data samples corresponding to an input data signal;
a hardware accelerator; and
a data interface coupled to the array of processing elements and to the hardware accelerator, the data interface being configured to transfer the array of data samples from the array of processing elements to the hardware accelerator,
wherein the hardware accelerator is configured to compute digital pre-distortion (DPD) parameters in accordance with a predetermined preprocessing function using the array of data samples transferred via the data interface; and
a power amplifier (PA) configured to transmit an output data signal based upon a set of preprocessed data samples that are generated using the DPD parameters.