US 12,314,196 B2
Memory device bandwidth optimization
Gregory S. Mathews, Saratoga, CA (US); and Shane J. Keil, San Jose, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Feb. 27, 2024, as Appl. No. 18/588,406.
Application 18/588,406 is a continuation of application No. PCT/US2022/040767, filed on Aug. 18, 2022.
Application PCT/US2022/040767 is a continuation of application No. 17/655,324, filed on Mar. 17, 2022, granted, now 11,914,532, issued on Feb. 27, 2024.
Claims priority of provisional application 63/239,361, filed on Aug. 31, 2021.
Prior Publication US 2024/0202146 A1, Jun. 20, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/16 (2006.01); G06F 1/06 (2006.01)
CPC G06F 13/1684 (2013.01) [G06F 1/06 (2013.01); G06F 13/1647 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory device that includes:
a plurality of memory bank circuits, a given memory bank circuit of the plurality of memory bank circuits including a respective set of memory cell circuits;
a command bus circuit configured to receive a plurality of memory commands;
a data bus circuit configured to transfer data to and from one or more of the memory cell circuits in response to ones of the plurality of memory commands; and
wherein the memory device is configured to:
receive, via the command bus circuit, a sync command executable to start a clock signal of the data bus circuit;
based on having received an indication of a sync delay, start the clock signal of the data bus circuit after a delay period; and
based on not having received the indication of the sync delay, start the clock signal of the data bus circuit without the delay period.