US 12,314,191 B2
Memory protection for vector operations
Krste Asanovic, Oakland, CA (US); and Andrew Waterman, Berkeley, CA (US)
Assigned to SiFive, Inc., Santa Clara, CA (US)
Appl. No. 18/024,262
Filed by SiFive, Inc., San Mateo, CA (US)
PCT Filed Sep. 1, 2021, PCT No. PCT/US2021/048634
§ 371(c)(1), (2) Date Mar. 1, 2023,
PCT Pub. No. WO2022/051345, PCT Pub. Date Mar. 10, 2022.
Claims priority of provisional application 63/073,916, filed on Sep. 2, 2020.
Prior Publication US 2023/0315649 A1, Oct. 5, 2023
Int. Cl. G06F 21/00 (2013.01); G06F 9/30 (2018.01); G06F 12/14 (2006.01); G06F 21/62 (2013.01); H04L 29/06 (2006.01)
CPC G06F 12/1458 (2013.01) [G06F 9/30036 (2013.01); G06F 21/6218 (2013.01); G06F 2212/1052 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An integrated circuit for executing instructions comprising:
a processor core including a pipeline configured to execute instructions, including constant-stride vector memory instructions;
a memory protection circuit configured to check for memory protection violations with a protection granule; and
a vector partition circuit configured to:
determine a maximum length, greater than one, corresponding to a number of vector elements to be accessed in a single clock cycle, wherein the maximum length is determined based on the protection granule and a stride of a vector that is identified by a vector memory instruction;
partition the vector into a subvector of the maximum length and one or more additional subvectors with lengths less than or equal to the maximum length;
check, using the memory protection circuit, whether accessing elements of the subvector will cause a memory protection violation; and
access the elements of the subvector before checking, using the memory protection circuit, whether accessing elements of one of the one or more additional subvectors will cause a memory protection violation.