| CPC G06F 12/1009 (2013.01) [G06F 12/0875 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/305 (2013.01)] | 19 Claims |

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1. A system, comprising:
a logical block address (LBA) cache memory circuit that stores a plurality of logical block addresses (LBAs) received from a host;
a mapping table cache memory circuit having a size, wherein:
the mapping table cache memory circuit stores at least one of a plurality of mapping tables;
the plurality of mapping tables stores mapping information between the plurality of LBAs and a plurality of physical addresses on a solid state storage; and
the size of the mapping table cache memory circuit is strictly smaller than a sufficient size to simultaneously store all of the plurality of mapping tables; and
a sorting electronic circuit that:
reads at least one of the plurality of LBAs from the LBA cache memory circuit to obtain a read LBA;
determines a group that the read LBA belongs to based at least in part on a predetermined grouping rule; and
determines (1) a quantity of groups in a plurality of groups, wherein the plurality of groups includes said group that the read LBA belongs to and (2) a quantity of data in each group in the plurality of groups after determining the group that the read LBA belongs to; and
writes LBAs belonging to a same group in the plurality of groups into a contiguous storage space of the LBA cache memory circuit.
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