US 12,314,175 B2
Cache memory with per-sector cache residency controls
Michael Fetterman, Lancaster, MA (US); Shirish Gadre, Fremont, CA (US); Steven James Heinrich, Madison, AL (US); Martin Stich, Memmingen (DE); and Liang Yin, Palo Alto, CA (US)
Assigned to NVIDIA CORPORATION, Santa Clara, CA (US)
Filed by NVIDIA CORPORATION, Santa Clara, CA (US)
Filed on Mar. 23, 2022, as Appl. No. 17/702,458.
Prior Publication US 2023/0305957 A1, Sep. 28, 2023
Int. Cl. G06F 12/0802 (2016.01)
CPC G06F 12/0802 (2013.01) [G06F 2212/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method for managing cache memory in a computing system, the method comprising:
detecting, by a cache controller, an instruction issued by a user mode software application executing on a processing unit and directed to the cache controller, wherein the instruction issued by the user mode software application directs the cache controller to invalidate a specified memory range, wherein the specified memory range is associated with a first sector in a first cache line of a cache memory;
determining a location of the first sector in the cache memory; and
upon detecting the instruction issued by the user mode software application executing on the processing unit, modifying a first status indicator associated with the first sector to generate a modified first status indicator while maintaining status indicators for a second sector in the first cache line, wherein the modified first status indicator invalidates the first sector.