| CPC G06F 11/1629 (2013.01) | 12 Claims |
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1. A semiconductor device comprising:
first and second processor cores configured to perform a lock step operation;
a first scan chain included in the first processor core;
a second scan chain included in the second processor core;
a scan test control unit that controls a scan test of the first and second processor cores using the first and second scan chains; and
a start-up control unit that outputs a reset signal for bringing the first and second processor cores into a reset state,
wherein the start-up control unit generates an initialization scan request before releasing the reset states of the first and second processor cores to start the lock step operation, and
wherein the scan test control unit performs, based on the initialization scan request, an initialization scan test operation on the first and second processor cores by using an initialization pattern.
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