US 12,314,116 B2
Systems and methods for adaptive power multiplexing
Giby Samson, San Diego, CA (US); Smeeta Heggond, Bagalkot (IN); Jitu Khushalbhai Mistry, San Diego, CA (US); Paras Gupta, San Diego, CA (US); Keyurkumar Karsanbhai Kansagra, Bangalore (IN); Kamesh Medisetti, Bangalore (IN); Ramaprasath Vilangudipitchai, San Diego, CA (US); and Arshath Sheeparamatti, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Appl. No. 18/000,319
Filed by QUALCOMM Incorporated, San Diego, CA (US)
PCT Filed Jul. 28, 2021, PCT No. PCT/US2021/043351
§ 371(c)(1), (2) Date Nov. 30, 2022,
PCT Pub. No. WO2022/026489, PCT Pub. Date Feb. 3, 2022.
Claims priority of application No. 202041032888 (IN), filed on Jul. 31, 2020.
Prior Publication US 2023/0221789 A1, Jul. 13, 2023
Int. Cl. G06F 1/26 (2006.01); G06F 1/3234 (2019.01); G06F 1/3296 (2019.01)
CPC G06F 1/3296 (2013.01) [G06F 1/263 (2013.01); G06F 1/3275 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A system on chip (SOC) comprising:
a first memory block and a second memory block;
a processing unit coupled to the first memory block and the second memory block;
a first power multiplexor disposed between the first memory block and the second memory block, and coupled to a first power rail configured to provide an operating voltage to both the first memory block and the second memory block;
enable logic circuitry disposed at a periphery of the SOC away from the first memory block and the second memory block, the enable logic circuitry being configured to control the first power multiplexer to select between a first power supply voltage and a second power supply voltage to provide the operating voltage to the first power rail; and
a voltage generator configured to provide a switching voltage to the first power multiplexor by a second power rail, wherein the first power multiplexor is configured to use the switching voltage to switch off transistors within the first power multiplexor.