| CPC G05F 1/467 (2013.01) [H01F 17/0006 (2013.01); H01F 27/2804 (2013.01); H01F 27/34 (2013.01)] | 20 Claims |

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1. A circuit layout for improving a power supply rejection ratio (PSRR), the circuit layout comprising:
a radio frequency (RF) choke including:
a first choke coil positioned in a first metal layer, the first choke coil including a first choke electrode; and
a second choke coil positioned in a second metal layer, the second choke coil including a second choke electrode; and
an inductor of a main circuit, the inductor including:
a primary-side coil including a first primary-side coil, a second primary-side coil, a first primary-side electrode, and a second primary-side electrode, wherein: both the first primary-side coil and the second primary-side coil are positioned in the first metal layer and surrounds the first choke coil; the first primary-side electrode is coupled with a choke positive electrode; the second primary-side electrode is coupled with a signal input circuit of the main circuit; when the second choke electrode functions as the choke positive electrode, the first choke electrode functions as a choke negative electrode and is coupled with a voltage supply terminal; and when the first choke electrode functions as the choke positive electrode, the second choke electrode functions as the choke negative electrode and is coupled with the voltage supply terminal; and
a secondary-side coil including a first secondary-side coil, a second secondary-side coil, a first secondary-side electrode, and a second secondary-side electrode, wherein: the first secondary-side coil is positioned in the first metal layer and surrounds the first choke coil; the second secondary-side coil is positioned in the second metal layer and surrounds the second choke coil; and both the first secondary-side electrode and the second secondary-side electrode are used for signal output,
wherein the RF choke and the inductor jointly form mutual induction to suppress a noise of a supply voltage of the voltage supply terminal.
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