US 12,313,948 B2
Active matrix substrate and liquid crystal display device
Atsushi Hachiya, Kameyama (JP); Hiroaki Furukawa, Kameyama (JP); Yuhichi Saitoh, Kameyama (JP); and Kuniaki Okada, Kameyama (JP)
Assigned to Sharp Display Technology Corporation, Kameyama (JP)
Filed by Sharp Display Technology Corporation, Kameyama (JP)
Filed on Apr. 10, 2024, as Appl. No. 18/631,940.
Application 18/631,940 is a continuation of application No. 17/978,312, filed on Nov. 1, 2022, granted, now 11,971,641.
Claims priority of application No. 2021-189605 (JP), filed on Nov. 22, 2021.
Prior Publication US 2024/0255822 A1, Aug. 1, 2024
Int. Cl. G02F 1/1368 (2006.01); G02F 1/1333 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01)
CPC G02F 1/1368 (2013.01) [G02F 1/134309 (2013.01); G02F 1/136286 (2013.01); H10D 86/441 (2025.01); H10D 86/60 (2025.01); G02F 1/133345 (2013.01); G02F 1/133388 (2021.01); G02F 1/13439 (2013.01); G02F 2201/48 (2013.01); G02F 2202/105 (2013.01); G02F 2202/16 (2013.01)] 3 Claims
OG exemplary drawing
 
1. An active matrix substrate provided with a display region defined by a plurality of pixel regions, the active matrix substrate comprising:
a substrate;
a transistor supported by the substrate and disposed on each of the plurality of pixel regions, the transistor including
an oxide semiconductor layer provided on the substrate, the oxide semiconductor layer including a channel region, a source contact region, and a drain contact region, the source contact region and the drain contact region positioned, respectively, at any one side of the channel region,
a gate insulating layer provided on the channel region, and
a gate electrode provided on the gate insulating layer and formed by a gate metal layer, the gate electrode facing the channel region with the gate insulating layer interposed between the channel region and the gate electrode;
an interlayer insulation layer covering the transistor, the interlayer insulation layer having a first contact hole located on the drain contact region;
a transparent connection electrode provided on the interlayer insulation layer and electrically connected to the drain contact region via the first contact hole, the transparent connection electrode including a first portion extending from the first contact hole to right above the gate metal layer, and a second portion extending opposite to the first portion;
an organic insulating layer covering the transistor and the transparent connection electrode, and having a second contact hole located on the first portion, a bottom of the second contact hole overlapping the gate metal layer when viewed from a normal direction of the substrate, a side surface of the second contact hole having a curved shape in a cross-sectional view; and
a pixel electrode provided on the organic insulating layer and electrically connected to the first portion of the transparent connection electrode via the second contact hole, the pixel electrode extending from the second contact hole beyond an end edge of the second portion of the transparent connection electrode.