US 12,313,682 B2
Method, system and device of serializing and de-serializing the delivery of scan test data through chip I/O to reduce the scan test duration of an integrated circuit
Sounil Biswas, San Jose, CA (US); Amit Wangoo, Cupertino, CA (US); and Zhanwei Zhong, Milpitas, CA (US)
Assigned to MARVELL ASIA PTE, LTD., Singapore (SG)
Filed by Sounil Biswas, San Jose, CA (US); Amit Wangoo, Cupertino, CA (US); and Zhanwei Zhong, Milpitas, CA (US)
Filed on Jul. 20, 2022, as Appl. No. 17/869,495.
Prior Publication US 2024/0027526 A1, Jan. 25, 2024
Int. Cl. G01R 31/3187 (2006.01); G06F 13/42 (2006.01)
CPC G01R 31/3187 (2013.01) [G06F 13/4282 (2013.01)] 30 Claims
OG exemplary drawing
 
1. An integrated circuit verification system, the system comprising:
an electronic device under test comprising:
one or more general-purpose input/output (I/O) ports;
a scan serializer including a serializer and a de-serializer, wherein an input of the de-serializer is coupled with the general-purpose I/O ports for serially receiving scan test data and an output of the serializer is coupled with the general-purpose I/O ports for serially outputting test response data; and
one or more circuits under test having a plurality of virtual I/O ports, wherein an output of the de-serializer is coupled with the virtual I/O ports for transmitting de-serialized scan test data to the circuits under test and an input of the serializer is coupled with the plurality of virtual I/O ports for non-serially inputting the test response data from the circuits under test; and
automatic test equipment having a memory and a processor and coupled with the device under test via the one or more general-purpose I/O ports, wherein the automatic test equipment is configured to generate the scan test for testing the device under test, serially transmit the scan test to the device under test via the one or more general-purpose I/O ports, serially receive the serial test response data via the one or more general-purpose I/O ports and analyze the serial test response data by comparing the serial test response data to expected response data stored on the memory.