US 11,991,939 B2
Method of manufacturing a memory device comprising introducing a dopant into silicon oxide
Yoshinori Kumura, Tokyo (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Dec. 12, 2022, as Appl. No. 18/079,161.
Application 18/079,161 is a division of application No. 17/016,155, filed on Sep. 9, 2020, granted, now 11,557,725.
Claims priority of application No. 2020-040607 (JP), filed on Mar. 10, 2020.
Prior Publication US 2023/0108500 A1, Apr. 6, 2023
Int. Cl. H10N 70/00 (2023.01); H10B 61/00 (2023.01); H01L 29/36 (2006.01)
CPC H10N 70/8833 (2023.02) [H10B 61/10 (2023.02); H10N 70/043 (2023.02); H10N 70/063 (2023.02); H10N 70/841 (2023.02); H01L 29/36 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A method of manufacturing a memory device including a silicon oxide and a variable resistance element electrically coupled to the silicon oxide, comprising:
introducing a dopant into the silicon oxide from a first surface of the silicon oxide by ion implantation;
thinning the silicon oxide by etching the first surface of the silicon oxide with an ion beam; and
removing a first part of the thinned silicon oxide to leave a second part of the thinned silicon oxide, after the thinning of the silicon oxide.