US 11,991,885 B2
Semiconductor memory devices and methods of fabricating the same
Sung-Min Hwang, Hwaseong-si (KR); Joon-Sung Lim, Seongnam-si (KR); and Eunsuk Cho, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Aug. 30, 2021, as Appl. No. 17/460,814.
Application 16/902,575 is a division of application No. 15/982,001, filed on May 17, 2018, granted, now 10,727,244, issued on Jul. 28, 2020.
Application 17/460,814 is a continuation of application No. 16/902,575, filed on Jun. 16, 2020, granted, now 11,107,828.
Claims priority of application No. 10-2017-0073390 (KR), filed on Jun. 12, 2017; and application No. 10-2017-0146813 (KR), filed on Nov. 6, 2017.
Prior Publication US 2021/0391349 A1, Dec. 16, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/40 (2023.01); H01L 25/065 (2023.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/50 (2023.01)
CPC H10B 43/40 (2023.02) [H01L 25/0657 (2013.01); H01L 29/4234 (2013.01); H01L 29/66833 (2013.01); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/50 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a first semiconductor chip and a second semiconductor chip, each semiconductor chip of the first semiconductor chip and the second semiconductor chip including
a cell array region, the cell array region including
an electrode structure including a plurality of electrodes sequentially stacked on a body conductive layer, and
a plurality of vertical structures extending through the electrode structure and connected to the body conductive layer, and
a peripheral circuit region, the peripheral circuit region including a residual substrate on the body conductive layer and on which a peripheral transistor is located,
wherein a bottom surface of the body conductive layer of the second semiconductor chip faces a bottom surface of the body conductive layer of the first semiconductor chip,
wherein the residual substrate includes a buried insulation layer in the peripheral circuit region, and the peripheral transistor is disposed on the buried insulation layer.