US 11,991,884 B1
3D semiconductor device and structure with logic and memory
Zvi Or-Bach, Haifa (IL); and Jin-Woo Han, San Jose, CA (US)
Assigned to Monolithic 3D Inc., Klamath Falls, OR (US)
Filed by Monolithic 3D Inc., Klamath Falls, OR (US)
Filed on Nov. 21, 2023, as Appl. No. 18/515,255.
Application 18/515,255 is a continuation in part of application No. 17/665,560, filed on Feb. 6, 2022.
Application 17/665,560 is a continuation in part of application No. 17/524,737, filed on Nov. 11, 2021, granted, now 11,296,115, issued on Apr. 5, 2022.
Application 17/524,737 is a continuation in part of application No. 17/396,711, filed on Aug. 8, 2021, granted, now 11,233,069, issued on Jan. 25, 2022.
Application 17/396,711 is a continuation in part of application No. 17/063,397, filed on Oct. 5, 2020, granted, now 11,114,464, issued on Sep. 7, 2021.
Application 17/063,397 is a continuation in part of application No. 16/526,763, filed on Jul. 30, 2019, granted, now 10,847,540, issued on Nov. 24, 2020.
Application 16/526,763 is a continuation in part of application No. 15/990,611, filed on May 26, 2018, granted, now 10,418,369, issued on Sep. 17, 2019.
Application 15/990,611 is a continuation of application No. 15/333,138, filed on Oct. 24, 2016, granted, now 10,014,318, issued on Jul. 3, 2018.
Claims priority of provisional application 62/307,568, filed on Mar. 14, 2016.
Claims priority of provisional application 62/286,362, filed on Jan. 23, 2016.
Claims priority of provisional application 62/276,953, filed on Jan. 10, 2016.
Claims priority of provisional application 62/271,251, filed on Dec. 27, 2015.
Claims priority of provisional application 62/266,610, filed on Dec. 12, 2015.
Claims priority of provisional application 62/246,054, filed on Oct. 24, 2015.
Int. Cl. H10B 43/27 (2023.01); H01L 23/528 (2006.01); H01L 27/02 (2006.01); H01L 29/167 (2006.01); H01L 29/47 (2006.01); H01L 29/78 (2006.01); H01L 29/792 (2006.01); H10B 41/10 (2023.01); H10B 41/20 (2023.01); H10B 43/10 (2023.01); H10B 43/20 (2023.01); H10B 53/20 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 23/5283 (2013.01); H01L 27/0207 (2013.01); H01L 29/167 (2013.01); H01L 29/47 (2013.01); H01L 29/7827 (2013.01); H01L 29/792 (2013.01); H10B 43/10 (2023.02); H10B 43/20 (2023.02); H10B 41/10 (2023.02); H10B 41/20 (2023.02); H10B 53/20 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors;
a first metal layer overlaying said first single crystal layer;
a second metal layer overlaying said first metal layer;
a third metal layer overlaying said second metal layer;
a plurality of second transistors disposed atop said third metal layer;
a plurality of third transistors disposed atop said plurality of second transistors;
a fourth metal layer disposed atop said plurality of third transistors; and
a memory array comprising word-lines,
wherein said memory array comprises at least four memory mini arrays,
wherein each of said memory mini arrays comprises at least four rows by at least four columns of memory cells,
wherein at least one of said plurality of second transistors comprises a metal gate,
wherein each of said memory cells comprises at least one of said plurality of second transistors or at least one of said plurality of third transistors, and
wherein said memory control circuit comprises at least one digital to analog converter circuit.