CPC H10B 43/27 (2023.02) [H01L 23/528 (2013.01); H10B 43/10 (2023.02); H10B 43/30 (2023.02); H10B 43/40 (2023.02)] | 20 Claims |
1. A vertical memory device comprising:
a memory cell array including a cell block including a first sub-cell block and a second sub-cell block arranged adjacent to each other and extending in a first direction; and
a block selector including a plurality of pass transistors for selecting the cell block;
wherein the cell block includes a gate line structure including a plurality of gate lines sequentially stacked on a substrate and including a plurality of protrusions connected to the plurality of pass transistors,
wherein first pass transistors of the plurality of pass transistors are connected to the first sub-cell block, and second pass transistors of the plurality of pass transistors are connected to the second sub-cell block,
wherein the plurality of protrusions protrude in a direction perpendicular to the first direction, and include first protrusions connected to the first pass transistors and second protrusions connected to the second pass transistors, and
wherein one of a first protrusion and a second protrusion disposed on the same layer from the substrate among the first protrusions and second protrusions protrudes in a second direction perpendicular to the first direction, and the other of the first protrusion and the second protrusion protrude protrudes in a direction opposite to the second direction.
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