US 11,991,876 B2
Method for forming a semiconductor structure having second isolation structures located between adjacent active areas
Junbo Pan, Hefei (CN); and Jinghao Wang, Hefei (CN)
Assigned to Changxin Memory Technologies, Inc., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Anhui (CN)
Filed on Jan. 7, 2022, as Appl. No. 17/570,483.
Application 17/570,483 is a continuation of application No. PCT/CN2021/117286, filed on Sep. 8, 2021.
Claims priority of application No. 202110768525.X (CN), filed on Jul. 7, 2021.
Prior Publication US 2023/0008414 A1, Jan. 12, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/482 (2023.02) 14 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor structure, comprising:
providing active areas and first isolation structures which are disposed at intervals;
forming second isolation structures located between adjacent active areas, top surfaces of the second isolation structures being higher than or flush with top surfaces of the active areas;
forming a mask layer, pattern openings of the mask layer exposing part of the top surfaces of the active areas, and the second isolation structures being located at two opposite sides of part of the active areas;
etching the part of the active areas exposed by the pattern openings and part of the first isolation structures to form intermediate grooves; and
forming bit line structures electrically connected to the top surfaces of the active areas exposed by the intermediate grooves.