US 11,991,873 B2
Capacitor separations in dielectric layers
Travis W. Lajoie, Forest Grove, OR (US); Abhishek A. Sharma, Hillsboro, OR (US); Van H. Le, Portland, OR (US); Chieh-Jen Ku, Hillsboro, OR (US); Pei-Hua Wang, Beaverton, OR (US); Jack T. Kavalieros, Portland, OR (US); Bernhard Sell, Portland, OR (US); Tahir Ghani, Portland, OR (US); Gregory George, Beaverton, OR (US); Akash Garg, Portland, OR (US); Julie Rollins, Forest Grove, OR (US); Allen B. Gardiner, Portland, OR (US); Shem Ogadhoh, Beaverton, OR (US); Juan G. Alzate Vinasco, Tigard, OR (US); Umut Arslan, Portland, OR (US); Fatih Hamzaoglu, Portland, OR (US); Nikhil Mehta, Portland, OR (US); Yu-Wen Huang, Beaverton, OR (US); and Shu Zhou, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 14, 2023, as Appl. No. 18/109,780.
Application 18/109,780 is a division of application No. 16/457,657, filed on Jun. 28, 2019, granted, now 11,610,894.
Prior Publication US 2023/0200043 A1, Jun. 22, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/03 (2023.02) [H10B 12/05 (2023.02); H10B 12/30 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor device, the method comprising:
forming a first inter-level dielectric (ILD) layer above a substrate;
forming a first bottom plate of a first capacitor and a second bottom plate of a second capacitor within the first ILD layer, wherein the first bottom plate and the second bottom plate are separated by a first dielectric area in the first ILD layer;
forming a first capacitor dielectric layer adjacent to and above the first bottom plate, and a second capacitor dielectric layer adjacent to and above the second bottom plate;
forming a first top plate of the first capacitor adjacent to and above the first capacitor dielectric layer, and a second top plate of the second capacitor adjacent to and above the second capacitor dielectric layer;
forming a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate, wherein the second dielectric area includes a dielectric material of the first ILD layer;
forming a second ILD layer above the first ILD layer to cover the first top plate, the second top plate, and the second dielectric area; and
forming a conductive segment following a part of a contour of the second dielectric area of the first ILD layer, wherein the conductive segment is to couple the first top plate and the second top plate, and wherein the conductive segment has a non-planar uppermost surface.