CPC H04W 68/02 (2013.01) [H04W 52/0229 (2013.01)] | 19 Claims |
1. A first apparatus comprising a processor, a memory, and communication circuitry, the first apparatus being capable of connecting to a communications network via its communication circuitry, the first apparatus further comprising computer-executable instructions stored in the memory of the first apparatus which, when executed by the processor of the first apparatus, cause the first apparatus to:
detect, from a second apparatus, one or more swept downlink beams,
wherein each swept downlink beam comprises a first number of synchronization signal blocks;
select a first synchronization signal block from the first number of synchronization signal blocks of each detected swept downlink beam;
receive, from the second apparatus, a paging configuration via system information, the paging configuration indicating a paging occasion comprising the first number of paging blocks including a first paging block,
wherein there is a one to one mapping between the first number of paging blocks and the first number of synchronization signal blocks,
wherein the first apparatus is configured to identify a first paging block associated with the first synchronization signal block by referring to the one to one mapping based on indications being informed to the first apparatus via system information;
monitor, based on the paging configuration, for paging indication transmitted as a paging control information in the first paging block associated with the first synchronization signal block,
wherein the paging indication indicates control resource set for the paging control information and the control resource set indicates quasi co-location of the paging indication with the first synchronization signal block; and
receive, based on the paging indication, a paging message.
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