CPC H04W 28/06 (2013.01) [H04L 1/0025 (2013.01); H04W 84/12 (2013.01)] | 15 Claims |
1. An apparatus of
an extremely high throughput (EHT) station (STA), the apparatus comprising memory; and processing circuitry coupled to the memory, the processing circuitry configured to:
decode, from an access point (AP), a first (PHY) protocol data unit (PPDU), the first PPDU comprising an individual/group bit of a media access control (MAC) individual address of the AP, the individual/group bit set to 1 indicating the first PPDU comprises a service field, the service field comprising a scrambler initialization field comprising a bit 0, a bit 1, a bit 2, a bit 3, a bit 4, a bit 5 and a bit 6 for initialization, wherein a transmit order indicates the bit 0 is to be transmitted first and a bit 15 is to be transmitted last, and wherein the service field further comprises a bit 7, wherein if the bit 7 is set to 0, a channel bandwidth (CBW) is 20 MHz, 40 MHz, 80 MHz, 160 MHz, or 80+80 MHz, and if the bit 5 is set to 0, the bit 6 is set to 0, and the bit 7 is set 1, the CBW is 320 MHz, wherein the first PPDU is a non-high throughput (non-HT) or non-HT duplicate PPDU;
encode a second PPDU in response to the first PPDU, the second PPDU encoded in accordance with the CBW; and
configure the EHT STA to transmit the second PPDU.
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