CPC H04N 9/67 (2013.01) [G06F 17/16 (2013.01); H04N 1/6027 (2013.01); H04N 1/6077 (2013.01); H04N 23/88 (2023.01)] | 18 Claims |
1. An apparatus, comprising:
a processor; and
a memory device external to the processor and comprising an internal image processor, wherein the internal image processor is configured to:
receive, from sensor circuitry, an input vector corresponding to an image pixel; and
perform a plurality of image signal processing stages that generate respective output vectors corresponding to the image pixel;
wherein the plurality of image signal processing stages comprise:
a defect correction stage;
a color interpolation stage subsequent to the defect correction stage; and
a white balance stage subsequent to the defect correction stage; and
wherein the plurality of image signal processing stages are performed on the memory device without moving image data corresponding to the image pixel from the memory device to the processor.
|