US 11,991,458 B2
Column arithmetic logic unit design for dual conversion gain sensor supporting correlated multiple sampling and three readout phase detection autofocus
Lihang Fan, Sunnyvale, CA (US); Nijun Jiang, Shanghai (CN); and Rui Wang, San Jose, CA (US)
Assigned to OmniVision Technologies, Inc., Santa Clara, CA (US)
Filed by OMNIVISION TECHNOLOGIES, INC., Santa Clara, CA (US)
Filed on Sep. 21, 2022, as Appl. No. 17/934,196.
Prior Publication US 2024/0098376 A1, Mar. 21, 2024
Int. Cl. H04N 25/75 (2023.01); H03M 1/12 (2006.01); H03M 1/18 (2006.01); H04N 23/76 (2023.01); H04N 25/78 (2023.01)
CPC H04N 23/76 (2023.01) [H03M 1/12 (2013.01); H03M 1/18 (2013.01); H03M 1/183 (2013.01); H04N 25/75 (2023.01); H04N 25/78 (2023.01)] 29 Claims
OG exemplary drawing
 
1. An arithmetic logic unit (ALU), comprising:
a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs of the GC generator in response to a comparator output;
a signal latch stage coupled to latch outputs of the front end latch stage in response to a signal latch enable signal;
a GC to binary stage coupled to generate a binary representation of the GC outputs latched in the signal latch stage;
an adder stage including first inputs and second inputs, wherein the first inputs of the adder stage are coupled to receive outputs of the GC to binary stage, wherein outputs of the adder stage are generated in response to the first inputs and the second inputs of the adder stage;
a pre-latch stage coupled to latch outputs of the adder stage in response to a pre-latch enable signal; and
a feedback latch stage coupled to latch outputs of the pre-latch stage, wherein the second inputs of the adder stage are coupled to receive outputs of the feedback latch stage, wherein the feedback latch stage comprises:
first conversion gain feedback latches configured to latch outputs of the pre-latch stage having a first conversion gain in response to a first feedback latch enable signal; and
second conversion gain feedback latches configured to latch outputs of the pre-latch stage having a second conversion gain in response to a second feedback latch enable signal.