US 11,991,399 B2
Apparatus and method for de-blocking filtering
Anand Meher Kotra, Munich (DE); Semih Esenlik, Munich (DE); and Zhijie Zhao, Munich (DE)
Assigned to Huawei Technologies Co., Ltd., Shenzhen (CN)
Filed by Huawei Technologies Co., Ltd., Shenzhen (CN)
Filed on Nov. 1, 2021, as Appl. No. 17/516,308.
Application 17/516,308 is a continuation of application No. 16/531,898, filed on Aug. 5, 2019, granted, now 11,184,643.
Application 16/531,898 is a continuation of application No. PCT/EP2017/057016, filed on Mar. 23, 2017.
Prior Publication US 2022/0060754 A1, Feb. 24, 2022
Int. Cl. H04N 19/86 (2014.01); H04N 19/117 (2014.01); H04N 19/176 (2014.01); H04N 19/82 (2014.01)
CPC H04N 19/86 (2014.11) [H04N 19/117 (2014.11); H04N 19/176 (2014.11); H04N 19/82 (2014.11)] 17 Claims
OG exemplary drawing
 
1. An apparatus for processing at least one frame of a video stream, the apparatus comprising:
a memory configured to store frames of the video stream; and
a processor configured to process a frame of the video stream stored in the memory using a block-based coding scheme that includes de-blocking filtering using a filter grid, wherein the processing of the frame of the video stream comprises coding or decoding;
wherein the processing includes dynamically determining a size FxW of the filter grid based on numbers of filter input and output samples during execution of the processing of the frame,
(a) wherein the filter output samples are samples modified by the processing,
(b) wherein F is larger than a sum of a maximum number of filter input samples of a de-blocking filter process of a vertical edge of a coding block and a maximum number of modified samples of the de-blocking filter process of the vertical edge of the coding block, and
(c) wherein W is larger than a sum of a maximum number of filter input samples of the de-blocking filter process of a horizontal edge of the coding block and the maximum number of modified samples of the de-blocking filter process of the horizontal edge of the coding block; and
wherein the processor is further configured to perform the de-blocking filtering on an edge of the coding block overlapping the filter grid, wherein the edge of the coding block overlapping the filter grid comprises the vertical edge of the coding block and/or the horizontal edge of the coding block.