US 11,991,376 B2
Switchable scalable and multiple description immersive video codec
Jill Boyce, Portland, OR (US); and Basel Salahieh, Santa Clara, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 9, 2021, as Appl. No. 17/226,510.
Claims priority of provisional application 63/007,859, filed on Apr. 9, 2020.
Prior Publication US 2021/0258590 A1, Aug. 19, 2021
Int. Cl. H04N 19/39 (2014.01); H04N 19/172 (2014.01); H04N 19/182 (2014.01)
CPC H04N 19/39 (2014.11) [H04N 19/172 (2014.11); H04N 19/182 (2014.11)] 20 Claims
OG exemplary drawing
 
1. A decoder system comprising:
a memory to store at least a portion of an immersive video of a bitstream comprising a plurality of pixel values each associated with an immersive video view, the bitstream comprising a first indicator indicating a switch between scalable coding and multiple descriptor coding to be used in a first portion of the immersive video and a second indicator indicating a switch between scalable coding and multiple descriptor coding to be used in a second portion of the immersive video; and
processor circuitry coupled to the memory, the processor circuitry to:
generate, in response to the first indicator indicating multiple descriptor coding, the first portion of the immersive video by merging first and second decoded pixel samples in the first portion; and
generate, in response to the second indicator indicating scalable coding, the second portion of the immersive video by summing third and fourth decoded pixel samples in the second portion.