US 11,991,356 B2
Deblocking filter control device and program
Shunsuke Iwamura, Tokyo (JP); Shimpei Nemoto, Tokyo (JP); and Atsuro Ichigaya, Tokyo (JP)
Assigned to NIPPON HOSO KYOKAI, Tokyo (JP)
Filed by NIPPON HOSO KYOKAI, Tokyo (JP)
Filed on Jan. 27, 2023, as Appl. No. 18/160,785.
Application 18/160,785 is a continuation of application No. 17/655,745, filed on Mar. 21, 2022, granted, now 11,595,645.
Application 17/655,745 is a continuation of application No. PCT/JP2021/014144, filed on Apr. 1, 2021.
Claims priority of application No. 2020-067043 (JP), filed on Apr. 2, 2020.
Prior Publication US 2023/0179765 A1, Jun. 8, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04N 19/117 (2014.01); H04N 19/146 (2014.01); H04N 19/184 (2014.01); H04N 19/82 (2014.01)
CPC H04N 19/117 (2014.11) [H04N 19/146 (2014.11); H04N 19/184 (2014.11); H04N 19/82 (2014.11)] 6 Claims
OG exemplary drawing
 
1. A deblocking filter control device that controls a process in a deblocking filter performed on a decoded image, in an encoding device that encodes a video signal or a decoding device that decodes an encoded video signal, the deblocking filter control device comprising:
a parameter deriver configured to derive a parameter value (tc′) that controls the process in the deblocking filter; and
a parameter transformer configured to output a transformed parameter value (tc) by transforming the parameter value (tc′) based on an input bit depth that is a bit depth of the video signal, wherein
when the input bit depth is smaller than a predetermined bit depth, the parameter transformer is configured to output the transformed parameter value (tc) by adding an offset value to the parameter value (tc′) and making a bit shift of a result of the addition, and
the parameter transformer is configured to change the offset value based on the input bit depth.