US 11,991,285 B2
Configurable cryptographic device
Oscar Garcia Morchon, Eindhoven (NL); Ludovicus Marinus Gerardus Maria Tolhuizen, Waalre (NL); Sauvik Bhattacharya, Eindhoven (NL); and Jose Luis Torre Arce, Eindhoven (NL)
Assigned to Koninklijke Philips N.V., Eindhoven (NL)
Filed by KONINKLIJKE PHILIPS N.V., Eindhoven (NL)
Filed on Jan. 12, 2023, as Appl. No. 18/096,040.
Application 18/096,040 is a continuation of application No. 16/755,899, filed on Apr. 14, 2020, granted, now 11,569,993.
Prior Publication US 2023/0163966 A1, May 25, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 9/30 (2006.01); H04L 9/08 (2006.01)
CPC H04L 9/3093 (2013.01) [H04L 9/0819 (2013.01); H04L 9/0838 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A first network node comprising:
a communication interface circuit, wherein the communication interface circuit is arranged to communicate with a second network node; and
a processor circuit,
wherein the processor circuit is arranged to receive a difficulty parameter (d), and a structure parameter (n),
wherein the processor circuit is arranged to obtain a shared matrix (A),
wherein the shared matrix (A) is shared with the second network node,
wherein the shared matrix (A) is a square matrix of dimension (k),
wherein dimension (k) is equal to the difficulty parameter (d) divided by the structure parameter (n),
wherein the shared matrix (A) comprises a plurality of shared matrix entries,
wherein at least a portion of the shared matrix entries are integer polynomials of degree less than the structure parameter (n),
wherein coefficients of the polynomials are selected modulo a first modulus (q),
wherein the processor circuit is arranged to generate a private key matrix (SI),
wherein the private key matrix (SI) comprises a plurality of private key entries,
wherein at least a portion of the private key entries are integer polynomials of degree less than the structure parameter (n),
wherein the processor circuit is arranged to generate a public key matrix (PI),
wherein the generation of the public key matrix (PI) comprises computing a public matrix product between the shared matrix (A) and the private key matrix (SI) modulo the first modulus (q) and modulo a reduction polynomial (ƒ),
wherein the reduction polynomial (f) has a degree,
wherein the degree is equal to the structure parameter (n),
wherein the public matrix product comprises a plurality of public matrix product entries,
wherein the processor circuit is arranged to add noise to at least a portion of the public matrix product entries, and
wherein the processor circuit is arranged to send the public key matrix (PI) to the second network node.