CPC H04L 5/005 (2013.01) [H04B 7/0695 (2013.01); H04L 5/0078 (2013.01); H04W 72/044 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
processor circuitry configured to:
determine a Synchronization Single Block (SSB) index for a SSB based on a candidate position in a set of candidate positions and a number of SSB beams;
determine a shift value for the SSB index based on the candidate position and the number of SSB beams; and
determine a frame timing for the SSB based the SSB index and the shift value for the SSB index; and
radio front end circuitry, coupled with the processor circuitry, configured to transmit the SSB to a user equipment (UE) based on the frame timing for the SSB.
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