CPC H04L 1/1861 (2013.01) [H04B 7/0426 (2013.01); H04B 7/0632 (2013.01); H04J 11/003 (2013.01); H04L 5/0048 (2013.01); H04L 5/005 (2013.01); H04L 5/0051 (2013.01); H04W 52/325 (2013.01); H04W 72/56 (2023.01); H04L 5/0007 (2013.01)] | 18 Claims |
1. An integrated circuit to control a process, the process comprising:
receiving a reference signal, the reference signal including:
a first type reference signal used in a first type of communication and a second type of communication mapped in all subframes including a first subframe, a second subframe and a third subframe; and
a second type reference signal used in the second type of communication mapped in the first subframe and the third subframe, wherein the second type reference signal is not mapped in the second subframe between the first subframe and the third subframe, and the second type reference signal is mapped such that a number of resources to which the second type reference signal is mapped per resource block is lower than a number of resources to which the first type reference signal is mapped per resource block;
computing a CQI based on at least one of the first type reference signal and the second type reference signal; and
transmitting the CQI.
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