CPC H04L 1/1812 (2013.01) [H04L 1/1803 (2013.01); H04L 1/1825 (2013.01); H04L 1/1848 (2013.01); H04L 1/188 (2013.01); H04L 1/1896 (2013.01); H04L 1/1887 (2013.01); H04L 1/203 (2013.01); H04W 72/54 (2023.01); H04W 76/27 (2018.02)] | 3 Claims |
1. An apparatus for wireless communication, comprising:
a processor;
memory coupled with the processor; and
instructions stored in the memory and executable by the processor to cause the apparatus to:
transmit or receive downlink control information (DCI) that schedules an uplink or downlink transmission of data;
transmit or receive, in the DCI, an indication that the uplink or downlink transmission is a final transmission of the data;
determine a block error rate (BLER) target of a type of service associated with the data;
allocate resources for the final transmission based at least in part on the BLER target, wherein the instructions to allocate the resources for the final transmission based at least in part on the BLER target are executable by the processor to cause the apparatus to:
identify a first amount of the resources to be used for the final transmission to satisfy the BLER target;
determine that a second amount of the resources available for the final transmission is less than the first amount of the resources; and
allocate less resources than the second amount of the resources for the final transmission; and
transmit or receive the data based at least in part on the DCI and the allocated resources for the final transmission of the data.
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